ASIC DV Modeling Engineer


  • Member of the IC Design Verification team
  • Drive all reference model development for IC verification including instrumentation, firmware development and verification specific algorithm development
  • Hands on participation in the verification process with considerable focus on extracting data needed for effective RTL validation
  • Primary interface between the Algorithm & IC Design Verification teams
  • Will act as the primary modeling resource for the IC design & verification teams
  • Will consult across teams on the technical details of video compression technologies

Minimum Requirements:

  • BSEE or BSCS degree
  • 5+ years of relevant industry work experience
  • Able to collaborate with all team members in the IC Design, DV, Algorithm & Software teams
  • Must have a solid understanding of IC design flows
  • Strong scripting skills in Python & Perl
  • Strong C/C++ programming language skills
  • SQL database experience
  • Experience with System Verilog/UVM/OVM/VMM a plus
  • Experience with video compression standards (MPEG-2, H.264 or HEVC)
  • Video compression standards committee developed reference model experience
  • Good communication skills and the ability to create technical documentation for design elements
  • Self-starter and effective team player in a dynamic start-up environment

Job site: Santa Clara, CA
Status: Full Time
Contact: Depending on your location, please submit resumes with the job title referenced, to: