Senior ASIC Design Engineer


  • Member of the video codec IC development team
  • Develop the video pipe micro-architecture to refine the processing and memory bandwidth requirements
  • Perform feasibility analysis on proposed implementations
  • Develop RTL for CODEC blocks and integrate into the overall SoC design
  • Work closely with the Design Verification team to meet overall test goals
  • Work with multi-disciplinary teams to emulate the design in both Palladium and FPGA platforms
  • Perform logic synthesis and make area/frequency/performance/power tradeoffs to meet the design goals
  • Own the design blocks through tape out
  • Participate in prototype IC bring-up, debug and system level testing
  • Work with Product Engineering as necessary to optimize test/performance elements to meet business targets

Minimum Requirements:

  • BSEE or BSCS degree (preferred), with of 8+ years of relevant industry work experience
  • Experience in RTL design (Verilog), verification, synthesis and timing closure
  • Prior experience in implementing video codecs particularly HEVC, H.264, & MPEG2
  • Experience with low power implementation techniques is a plus
  • Coding skills in Python, Perl or other industry-standard scripting languages is a plus
  • Strong technical leadership skills to drive architectural and implementation issues for individual blocks and top level design
  • Ability to work with multi-disciplinary teams to define the architecture, implement the design and assist production needs as required
  • Good communication skills and the ability to create technical documentation for design elements
  • Self-starter and effective team player in a dynamic start-up environment

Job site: Santa Clara, CA
Status: Full Time
Contact: Depending on your location, please submit resumes with the job title referenced, to: